1. Field
Embodiments of the present disclosure generally relates to biasing circuits and more particularly to a DC biasing circuit for a Metal Oxide Semiconductor (MOS) transistor for achieving low voltage, high swing, and high efficiency performance.
2. Prior Art
Biasing is done to setup initial voltages and currents in transistor circuits to establish an appropriate quiescent point. Various biasing circuits are used to bias a MOS transistor. In a conventional biasing circuit, a resistor (R) is DC coupled to the MOS transistor and an input signal is AC coupled through a capacitor (C). For example, in a current mirror circuit configuration as depicted in the prior art of FIG. 1, a source transistor 110 is mirrored to a mirror transistor 105. The mirroring includes coupling the gate of the source transistor 110 and the gate of the mirror transistor 105. The source transistor 110 is provided with a current source 125. The resistor 115 couples the source transistor 110 to the mirror transistor 105 and the capacitor 120 ac couples the input signal.
The RC combination forms a high pass filter for the signal. In such a combination, value of the resistor has to be large in order to achieve a low high pass corner frequency. With the large resistor value, gate leakage or any leakage can cause significant error in the transistor biasing.
The implementation of the resistor using active elements like MOS transistor and diode results in a large input signal swing which causes the resistance to vary and result in poor signal to noise at amplifier output, and a high distortion. The startup time also can be large due to the use of a large resistor to set a DC bias.
In light of the foregoing discussion, there is a need for efficient DC biasing circuit for a MOS transistor.
Hence, it is an objective of the present disclosure to provide an improved circuit for DC biasing of a Metal Oxide Semiconductor (MOS) transistor with good performance for large input signals and insensitive to leakages at the transistor input.